ZENG Qingyu

ZENG Qingyu

PhD Candidate

Tokyo Institute of Technology

Biography

I’m currently a PhD Candidate in Hara Lab at Tokyo Tech, supervised by Prof. Yuko Hara. I’m now working on FPGA-based ML accelerator design for IoT security scene. This homepage is built with Hugo template. I’m now updating it.

Interests
  • FPGA
  • Efficient Machine Learning
  • Embedded System
  • IoT Intrusion Detection
  • RISC-V
  • Computer Architecture
Education
  • PhD in Information and Communications Engineering, 2023-2026

    Tokyo Institute of Technology

  • MEng in Information and Communications Engineering, 2021-2023

    Tokyo Institute of Technology

  • BEng in VLSI Design & System Integration, 2017-2021

    Nanjing University

Skills

microchip
Hardware

FPGA application, AI accelerator design

python
Algorithm

Machine learning

shield-halved
Network Intrusion Detection

DL-based NIDS, FPGA-accelerated NIDS

Professional Experience

 
 
 
 
 
Research Assistant
Tokyo Institute of Technology
Jul 2022 – Present Tokyo, Japan
I work as research assistant for both school of engineering and Green-niX project.
 
 
 
 
 
Research Intern
Polytechnique Montreal
Feb 2023 – Jun 2023 Montreal, Canada

I worked as a short-term researcher, under supervision of Prof. Jean Pierre DAVID. My major research content included:

  • Matrix mutiplication optimization study
  • Algorithm prototype implementation
  • Hardware design with Verilog

Accomplish­ments

2023 SLDM Work-in-progress (WIP) Best Presentation Award
See certificate