Biography
I’m currently a PhD student in Hara Lab at Tokyo Tech, supervised by Prof. Yuko Hara. I’m now working on FPGA-based ML accelerator design for IoT security scene.
Interests
- FPGA
- Efficient Machine Learning
- Embedded System
- Internet of Things
- Intrusion Detection System
- Computer Architecture
Education
PhD in Information and Communications Engineering, 2023.10 ~ present
Tokyo Institute of Technology
MEng in Information and Communications Engineering, 2021.10 ~ 2023.09
Tokyo Institute of Technology
BEng in VLSI Design & System Integration, 2017.09 ~ 2021.06
Nanjing University
Skills
Hardware
FPGA application, AI accelerator design
Algorithm
Machine learning
Network Intrusion Detection
DL-based NIDS, FPGA-accelerated NIDS
Professional Experience
Research Assistant
Tokyo Institute of Technology
I work as a research assistant for Trustworthy Architecture, Cryptography, and Evaluation for IoT systems and Green-niX.
Research Intern
Polytechnique Montreal
I worked as a short-term researcher, under supervision of Prof. Jean Pierre DAVID. My major research content included:
- Matrix mutiplication optimization study
- Algorithm prototype implementation
- Hardware design with Verilog
Accomplishments
2023 SLDM Work-in-progress (WIP) Best Presentation Award
See certificate
Recent Publications
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(2024).
Hardware/Software Codesign of Real-Time Intrusion Detection System for Internet of Things Devices.
IEEE Internet of Things Journal, 2024. (*accepted).
(2024).
FPGA-Accelerated Random Forest for Real-Time IoT Intrusion Detection.
IEICE Tech. Rep., vol. 123, no. 374, RECONF2023-100, pp. 99-104, Jan. 2024.